Primary Memory

Primary memory is the memory that can be directly accessed by the CPU which constantly interacts with it, retrieves data stored therein, goes through instructions and execute them as per the requirement. All the information, data and application are loaded there in uniform manner. Earlier William tubes, delay lines or rotating magnetic drums were used as primary storage which were later replaced by magnetic core memory. Solid-state silicon chip technology revolutionized the electronic memory and paved the way for Random Access Memory (RAM). RAM is volatile (temporary) but fast form of memory.


Apart from the main large capacity Random Access Memory (RAM), there are two sub-layers of the primary memory.

Processor registers within the processor, which are one of the fastest forms of data storage, contain a word of data (usually 32 or 64 bits). The CPU instructs and helps the Arithmetic and logic unit to perform a number of calculations on this data.

Processor cache, which is meant for enhancing the performance of the computer, links the fast registers to the slower main memory. Cache memory loads the duplicated information that is used most actively. It is much faster than the main memory but relatively can store limited data. It is also much slower but much larger than the processor registers. Cache setup is further split into different levels with smallest and fastest primary cache and relatively larger but slower secondary cache.

The most familiar form of system memory, Random Access Memory (RAM) derives its name from the fact that any of its memory cells can be accessed directly if you are aware of the row and column that intersect at that cell. The columns are referred to as bitlines while the rows are referred to as wordlines. The intersection of a wordline and bitliine is the address of the memory cell onto a silicon wafer.

In case of Serial Access Memory (SAM), the opposite of RAM, the data is stored as a series of memory cells and can be accessed sequentially whereas data stored in RAM can be accessed in any order.

Bus width and bus speed control the RAM speed. The number of bits that can be sent to the CPU at the same point of time is referred to as bus width while the number of times a group of bits can be sent each second is referred to as bus speed. A bus cycle takes place as the information moves from the system memory to the CPU.
With latency (the number of clock cycles needed to read a bit of data) changing the equation thoroughly, RAM, generally, does not operate at optimum speed.

Burst mode hinges on the anticipation that the information required by the CPU will be loaded in sequential memory cells. The memory controller reads a number of consecutive bits of information together as it expects that the working of the CPU will keep coming from this same series of memory addresses. In this manner only the first bit is affected by the latency and the successive ones take much lesser time. The four number with dashed between them denote the rated burst mode of the system memory. The first one gives information about the number of clock cycles required to commence a read operation while the rest of the numbers inform about the wordline which are the number of cycles that are needed to read each consecutive bit in the row.

Pipelining, together with the burst mode is also used to minimize the effects of latency dramatically. It enables the memory controller to read from the memory, send the data to the CPU and write it to memory cells simultaneously.

Some common types of RAM are as follows:

SRAM: Used primarily to create CPU’s speed-sensitive cache, Static Random Access memory (SRAM) uses multiple transistors for each memory cell. It does not have a capacitor in each cell.

Each bit of memory is held by a flip-flop memory which takes four to six transistors besides some wiring. SRAM is not required to be refreshed which makes it significantly fast. As compared to DRAM, SRAM has more parts and therefore it consumes a lot more space on a chip. With less memory available per chip, the SRAM becomes costlier.

DRAM: Dynamic Random Access Memory needs to be refreshed consistently and contains memory cells with a paired transistor. In order to activate the transistor at each bit in the column, DRAM sends a charge through the appropriate column (CAS).

The level of charge is determined by the sense-amplifier while reading. If the level of charge exceeds fifty percent, it is read as a 1 whereas if the charge is below fifty percent it is read as a 0. For dynamic memory to work, Either the CPU or the memory controller recharges all the capacitors before they are discharged to zero.
To ensure this the memory is read and written back which if referred to as refresh operation. DRAM is required to be refreshed dynamically all the time otherwise it will lose the information. This refreshing operation consumes a lot of time and causes the memory to slow down.

The refresh sequence is tracked by the counter after determining the order in which the rows have been accessed. The time required to do the entire task is expressed only in nanoseconds. A memory chip rating of 100 nanosecond will mean than it take 100 nanoseconds to read each cell completely and recharge them.

Memory cells have a support infrastructure of other specialized circuits so that information can be put in and retrieved from them. These circuits identify each and column, keep track of the refresh sequence, read and restore the signal from a cell and tell a cell whether it should take a charge or not.

SDRAM: Synchronous dynamic random access memory enhances the system’s performance by utilizing the burst mode concept. With maximum transfer rate to L2 cache of 528 mbps, SDRAM stays on the row that contains the requested bit and moves quickly through the columns to read each bit as it moves on.

FPM DRAM: The pristine form of DRAM, Fast Page Mode Dynamic Random Access memory waits through the process of locating a bit of data by column and row and then reading the bit and then starts on the next bit. It has a maximum transfer rate to L2 cache of about 176 mbps.

EDO DRAM: Contrary to FPM DRAM, Extended data-out dynamic random access memory does not wait and as the address of the first bit is located it starts looking for the next bit. With maximum transfer rate to L2 cache of about 264 mbps, it is 5 percent faster than the FPM.

RDRAM: Rambus dynamic random access memory uses a special high speed data bus called the Rambus channel. It generates more heat than other chips as they operate at high speeds.

DDR SDRAM: Double data rate synchronous dynamic random access memory is somewhat similar to SDRAM but has higher bandwidth. It has a maximum transfer rate to L2cache of about 1064 mbps.

ROM

Read Only Memory (ROM) is an integrated circuit programmed with data that holds instructions for starting up the computer. Data stored in ROM is non volatile and is not lost when powered off. These data cannot be changed or a special operation is needed to be performed to change it.

ROM chips also comprise of columns and rows but it is different from RAM in terms of intersection of these. These chips use diodes instead of transistors to connect the lines if the value is 1 whereas if the value is 0 the lines are not connected.

A diode has the property of letting the current flow in one direction. It also has a threshold, called forward breakover, which is used to ascertain the current required. After the required flow of current the diode passes it on.

Voltage of the memory chips’ forward breakover hover around 0.6 volts. Using the diode, a chip can send a charge that is above the forward breakover to the appropriate column with the selected row grounded to connect at a particular cell. If the charge is conducted through to the ground, in presence of the diode at the intersection, the cell will be read as a 1. On the other hand if the value of the cell is zero, there is no diode at the intersection to establish the connection between the column and the row.

A ROM chip cannot be reprogrammed or rewritten therefore when the chip is created it requires the programming of perfect and complete information. ROM chips are cost effective and use very little power.

PROM

Programmable read only memory (PROM) is a type of ROM. These chips are non volatile and cannot be purged to store something else once it has been used. Blank PROM chips can be coded with the help of a tool known as a programmer.

Similar to ROM, PROM chips also have a grid of rows and columns but here fuses connect the intersections.

A Programmable read only memory chip.

A charge towards the columns passes through the fuse in a cell to a grounded row and indicates a value of 1. Initially PROM chips are all 1s for all cells have a fuse. In order to change the value of a cell to 0, a programmer is used to send the current to the cell. The connection between the column and the row snaps as the higher voltages while passing through burns out the fuse.

EPROM

Erasable Programmable Read Only Memory can be erased with the help of ultraviolet light and rewritten many times. These chips are configured by the EPROM programmer, providing the voltage at the specified levels. The floating gate is linked to the row through the control gate. The cell has a value of 1 till the link remains established. A process known as Fowler-Nordheim tunneling is performed to change the value to zero. The tunneling changes the placement of electrons in the floating gate. An electrical charge of 10 to 13 volts is passed through the bitline which drains to a ground after entering the floating gate.

The electrical charge excites the electrons of the transistor at the floating gate and they are pushed through and trapped on the side of the flimsy oxide layer to give a negative charge. A call sensor monitors the level of the charge that passes through the threshold of floating gate. Is shows a value of 1 if the flow is more than fifty percent. On the other hand if the flow is below fifty percent, the value change to 0. Blank EPROM chips have a value of 1 for each cell as the have all of the gates opened completely.

EEPROM

Electrically Erasable Programmable Read Only Memory chips are not required to removed to be erased or rewritten. These chips do not require to be erased altogether and specific portion of it can be easily altered. Additional dedicated equipment are also not required to change the content the EEPROM chips. These chips are erased and rewritten with the help of electric charge.